| Course Unit Code | Course Unit Title | Type of Course Unit | Year of Study | Semester | Number of ECTS Credits | | 180103007105 | DIGITAL CIRCUIT DESIGN | Elective | 4 | 7 | 5 |
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| Level of Course Unit |
| First Cycle |
| Objectives of the Course |
| This practical, hands-on course introduces digital logic design, system-level design using current state of the art in EDA tools used by professionals in VLSI field today. Students learn to design large-scale logic circuits from fundamental building blocks and methods. |
| Name of Lecturer(s) |
| Doç.Dr. Kenan ÇİÇEK |
| Learning Outcomes |
| 1 | Adequate knowledge in digital system design concepts. | | 2 | Ability to design and implement digital circuits under realistic constraints and conditions. | | 3 | Ability to debug, verify, simulate, synthesize digital circuits. | | 4 | Ability to devise, select, and use modern techniques and tools needed for digital system design. | | 5 | Ability to work in a team. |
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| Mode of Delivery |
| Daytime Class |
| Prerequisites and co-requisities |
| No |
| Recommended Optional Programme Components |
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| Course Contents |
| Brief summary of digital electronic circuits
Proteus electronic circuit simulation program introduction
Proteus-based sample circuit designs and circuit designs
Printed Circuit Board Printing techniques |
| Weekly Detailed Course Contents |
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| 1 | Introduction of circuit design simulation program | | | | 2 | Introduction of circuit design simulation program | | | | 3 | Introduction of circuit design simulation program | | | | 4 | Circuit simulation in computer environment with logic gates | | | | 5 | Circuit simulation in computer environment with logic gates | | | | 6 | Circuit simulation in computer environment with logic gates | | | | 7 | Circuit simulation in computer environment with logic gates | | | | 8 | Term project process observation meeting | | | | 9 | Term project process observation meeting | | | | 10 | Term project process observation meeting | | | | 11 | Term project process observation meeting | | | | 12 | Term project process observation meeting | | | | 13 | Term project process observation meeting | | | | 14 | Evaluating term projects | | |
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| Recommended or Required Reading |
| ART OF HARDWARE ARCHITECTURE BY MOHIT ARORA, SPRINGER.
FPGA PROTOTYPING BY VERILOG EXAMPLES BY PONG P. CHU, WILEY.
MODERN VLSI DESIGN BY WAYNE WOLF, PRENTICE-HALL |
| Planned Learning Activities and Teaching Methods |
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| Assessment Methods and Criteria | |
| Project Preparation | 1 | 40 | | Project Presentation | 1 | 20 | | SUM | 60 | |
| Report Presentation | 1 | 20 | | Project Preparation | 1 | 20 | | SUM | 40 | | Term (or Year) Learning Activities | 40 | | End Of Term (or Year) Learning Activities | 60 | | SUM | 100 |
| | Language of Instruction | | Turkish | | Work Placement(s) | | No |
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| Workload Calculation |
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| Project Preparation | 5 | 20 | 100 |
| Project Presentation | 6 | 6 | 36 |
| Homework | 5 | 5 | 25 |
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| Contribution of Learning Outcomes to Programme Outcomes |
| LO1 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | | LO2 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | | LO3 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | | LO4 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | | LO5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 | 5 |
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| * Contribution Level : 1 Very low 2 Low 3 Medium 4 High 5 Very High |
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Iğdır University, Iğdır / TURKEY • Tel (pbx): +90 476
226 13 14 • e-mail: info@igdir.edu.tr
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